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82571EB/82572ei gigabit ethernet controller networking silicon product datasheet revision 1.2 august 2006
ii product datasheet any intellectual property rights is granted by this document. except as provided in intel's terms and conditions of sale for such products, intel assumes no liability whatsoever, and intel disclaims any express or implied warranty, relating to sale and/or use of intel produc ts including liability or warranties relating to fitness for a particular purpose, merchantability, or infringement of any pa tent, copyright or other intellectual property right. intel products are not intended for use in medical , life saving, or life sustaining applications. intel may make changes to specifications and pr oduct descriptions at any time, without notice. designers must not rely on the absence or ch aracteristics of any features or instructions marked "reserved" or "undefined." int el reserves these for future definition and shall have no responsibility whatsoever for conflicts or incompatibilities arising from future changes to them. the intel product(s) referenced in this doc ument may contain design defects or errors known as errata which may cause the produ ct to deviate from published specifications. current characterize d errata are available on request. mpeg is an international standard for video compression/decompre ssion promoted by iso. implementations of mpeg codecs, or mpeg enabled platforms may require licenses from various en tities, including intel corporation. contact your local intel sales of fice or your distributor to obtain the latest specifications and before placing your product o rder. copies of documents which have an order num ber and are referenced in this document, or other intel literature may be obtained b y calling 1-800-548-4725 or by visiting intel's website at http://www.intel.com. intel? is a trademark or registered trademark of intel corporation or its su bsidiaries in the united states and other countries . copyright ? intel corporation, 2003 - 2006 *other names and brands may be claimed as the property of others.
product datasheet iii 82571EB/82572 gigabit ethernet controller revision history date revision notes oct 2002 0.15 initial release feb 2003 0.5 revised ballout, added package drawing, added visual pin descriptions, changed some ball names to ?exp? ball naming convention. aug 2003 0.6 ? updated power specifications. ? changed names to ?pe? naming convention ? revised signal descriptions, pinout information tables, and ballout grid. ? modified lan disable ballout to cover a-0 (dev_dis_n) and b-0 (dev_off_n). ? removed integrated basebo ard management controller. oct 2003 0.75 ? updated operating temperature ? changed dev_dis_n pin (a stepping) to rsvd_nc ? corrected led descriptions in signal descriptions in signal descriptions ? added absolute maximum ratings ? added general operating conditions ? added power specifications ? added voltage ramp and sequencing recommendations ? added dc i/o specifications ? added timing specifications ? edited thermal characteristics may 2004 0.85 ? section 4.4, figure 2; section 4.5.1.1;s ection 4.5.1.2, figure 5; section 4.5.2, figure 6; section 5.1, figure 7; section 5.1, figure 8; section 5.4, figure 9, ball t6 changed to perst_n. january 2005 0.90 ? included 82572ei information ? updated signal names ? updated power numbers may 2005 0.92 ? corrected 1.1v operating range in table 2 nov 2005 1.0 ? changed document status to ?intel conf idential,? updated power values, made minor corrections to text march 2006 1.1 ? corrected pinlists ? pin a7 device_dis_n has been moved to reserved and no connect signals; this pin is now reserved. refer to 82571EB/82571ei design guide for guidance on proper connection. ? pin r4 lan_pwr_good has been moved to reserved and no connect signals; this pin is now reserved. refer to 82571EB/82571ei design guide for guidance on proper connection. august 2006 1.2 ? corrected signal mames, minor text corrections
82571EB/82572 gigabit ethernet controller iv product datasheet contents 1.0 introduction................................................................................................................ ..................... 1 1.1 document scope.............................................................................................................. ... 1 1.2 reference documents......................................................................................................... 2 1.3 block diagram............................................................................................................... ..... 3 2.0 features of the 82571EB/82572ei gigabit ethernet controller ................................................ 5 2.1 pci express features........................................................................................................ .. 5 2.2 mac-specific features ...................................................................................................... 5 2.3 phy specific features.............. ......................................................................................... .6 2.4 host offloading features.................................................................................................... 6 2.5 manageability features...................................................................................................... .7 2.6 additional device features ................................................................................................ 7 2.7 technology features......................................................................................................... .. 8 3.0 signal descriptions......................................................................................................... ................. 9 3.1 signal type definitions..................................................................................................... .9 3.2 pci express interface ....................................................................................................... .. 9 3.3 power management signals ............................................................................................. 10 3.4 smb and fast management link bus signals ................................................................. 10 3.5 eeprom and serial flash in terface signals ........... .............. ............... .............. ......... 11 3.6 led signals................................................................................................................. ..... 11 3.7 other signals ............................................................................................................... ..... 12 3.8 crystal signals ............................................................................................................. ..... 12 3.9 phy analog signals......................................................................................................... 1 2 3.10 serializer / deserializer signals................... ..................................................................... 14 3.11 test interface signals . .............. .............. .............. .............. ........... ............ ........... .......... .. 14 3.12 power supply connections............................................................................................... 15 3.12.1 digital and analog supplie s ............... .............. .............. .............. .............. ....... 15 3.12.2 grounds, reserved pins and no connects......................................................... 15 4.0 voltage, temperature, and timing specifications .................................................................... 17 4.1 targeted absolute maximum ratings.............................................................................. 17 4.2 targeted recommended operating conditions ............................................................... 18 4.2.1 general operating conditions................ ............................................................ 18 4.2.2 voltage ramps ................................................................................................... 19 4.2.3 voltage power sequencing options................................................................... 20 4.3 dc specifications ........................................................................................................... .. 20 4.3.4 power specifications--82571 eb ............ .............. .............. .............. ........... ....... 21 4.3.5 power specifications--82572 ei.............. .............. .............. .............. ........... ....... 23 4.3.6 i/o characteristics.............................................................................................. 25 4.4 targeted ac characteristics............................................................................................. 26 4.5 targeted timing specifications......................... ............................................................... 28 4.5.1 pci express interface......................................................................................... 28 4.5.2 eeprom interface ............................................................................................ 31 4.5.3 flash interface ................................................................................................ 33
product datasheet v 82571EB/82572 gigabit ethernet controller 5.0 package and pinout information.............................................................................................. ....35 5.1 package information......................................................................................................... .35 5.2 thermal specification ....................................................................................................... 37 5.3 pinout information.......................................................................................................... ...37 5.4 visual pin assignments.....................................................................................................5 0
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product datasheet 1 82571EB/82572ei gigabit ethernet controller 1.0 introduction the intel 82571EB gigabit ethernet controller is a single, compact component with two fully integrated gigabit ethernet media access control (mac) and physical layer (phy) ports. the intel 82572ei gigabit ethernet controller is a si ngle-port version of the controller in the same package. these devices use the pci express* ar chitecture (rev. 1.0a). the intel 82571EB/82572ei enables dual- or single-port gigabit ethernet impl ementation in a very small area and can be used for server and workstation network de signs with critical space constraints. the intel 82571EB/82572ei provides a standard ieee 802.3 et hernet interface for 1000base-t, 100base-tx, and 10base-t applications (802.3, 802.3u, and 802.3ab). ports also contain a serializer-deserializer (serdes) to support 1000base-sx/lx (optical fiber) and gigabit backplane applications. in addition to managing mac and phy ethernet layer functions, the controller manages pci express pa cket traffic across its transacti on, link, and physical/logical layers. the intel 82571EB/82572ei?s on-board system management bus (smb) ports enable network manageability implementations required by inform ation technology personnel for remote control and alerting via the lan. with smb, management packets can be routed to or from a management processor. the smb ports enable industry standards, such as alert standard format (asf) 2.0, to be implemented using the 82571EB/82572ei contro ller. in addition, on-chip asf 2.0 circuitry provides alerting and remote control capabilities with standardized interfaces. enhanced pass- through capabilities also allow system remo te control over standardized interfaces. the 82571EB/82572ei gigabit ethernet controller with pci express architecture is designed for high performance and low memory latency. the device is optimized to connect to a system memory control hub (mch) using four pci express lanes. alternatively, the 82571EB/82572ei controller can connect to an i/o control hub (ich6 & 7) th at has a pci express interface. wide internal data paths eliminate performance bottlenecks by efficiently handling large address and data words. combining a parallel and pipe -lined logic architectur e optimized for gigabit ethernet and independent transmit and receive queues, the 8 2571eb/82572ei cont roller efficiently handles packets with minimum latency. the 82571EB/82572ei controller includes advanced interrupt handling features. the 82571EB/82572ei uses efficient ring buffer descriptor data structures, with up to 64 packet descriptors cached on chip. a la rge 48 kbyte per port on-chip packet buffer maintains superi or performance. in addition, using hardware acceleration, the controller offloads tasks from the host, such as tcp/udp/ip checks um calculations and tcp segmentation. the 82571EB/82572ei is packaged in a 17 mm x 17 mm, 256-ball grid array. 1.1 document scope this document contains targeted datasheet specifications for the 82571EB/82572ei gigabit ethernet controller, including signal descriptions, dc and ac parameters, packaging data, and pinout information.
82571EB/82572 gigabit ethernet controller 2 product datasheet 1.2 reference documents this application assumes that the designer is acquainted with high-speed design and board layout techniques. the following documents provide additional information: ? 82571EB/82572ei gigabit ethernet controller design guide, ap-447. intel corporation. ? intel ethernet controllers timing device selection guide, ap-419. intel corporation. ? pci express base specification, revision 1.0a. pci special interest group. ? pci express card electromechani cal specification, revision 1.0a . pci special interest group. ? pci bus power management interface specificatio n, revision 1.1. pci special interest group. ? ieee standard 802.3, 2000 editio n. institute of electrical an d electronics engineers (ieee). this version incorporates various ieee standards previously published separately.
product datasheet 3 82571EB/82572ei gigabit ethernet controller 1.3 block diagram figure 1. 82571EB/82572ei gigabit ethernet controller block diagram (single port shown) pcie core pcie interface eeprom flash dma engine packet buffer tx mac (10/100 / 1000 mb) rx mac (10/100 / 1000 mb) packet / manageability filter tx switch asf manageability gmii / mii link i /f mdio mdio rmon statistics sm bus host arbiter
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product datasheet 5 82571EB/82572ei gigabit ethernet controller 2.0 features of the 82571EB/82572ei gigabit ethernet controller 2.1 pci express features 2.2 mac-specific features features benefits uses x4 pci express interface on mch device ? bus sharing not required ? low latency path to memory ? relieves congestion for io devices peak bandwidth 2 gb/s in each direction per pci express lane ? supports gigabit ethernet at full wire speed pci express power management ? compatible extensions to pci power management and acpi ? pe_wake_n available for wakeup event high bandwidth density per pin ? less congested board routing features benefits optimized transmit and receive queues ? network packets handled without waiting or buffer overflow. ieee 802.3x compliant flow control support with software controllable pause times and threshold values ? control over the transmissi ons of pause frames through software or hardware triggering ? frame loss reduced from receive overruns caches up to 64 packet descriptors (per qu eue) ? efficient use of pci express bandwidth separate transmit queue per port ? e fficient packet prioritization programmable host memory recei ve buffers (256 bytes to 16 kbytes) and cache line size (64 bytes to 128 bytes) ? efficient use of pci express bandwidth wide, pipelined internal data path architecture ? low latency data handling ? superior dma transfer rate performance dual 48 kbyte configurable transmit and receive fifo buffers ? no external fifo memory requirements ? fifo size adjustable to application descriptor ring management hardware for transmit and receive ? simple software programming model optimized descriptor fetchi ng and write-b ack mechanisms ? efficient system memory and use of pci express bandwidth mechanism available for redu cing interrupts generated by transmit and receive operations ? maximizes system performance and throughput supports transmission and reception of pa ckets up to 9 kb ? enables jumbo frames
82571EB/82572 gigabit ethernet controller 6 product datasheet 2.3 phy specific features 2.4 host offloading features features benefits integrated phy for 10/100/1000 mbps operation ? smaller footprint and lower power dissipation compared to multi-chip mac and phy solutions ieee 802.3ab auto-negotiation support ? automatic link configuratio n including speed, duplex, and flow control ieee 802.3ab phy compliance and compatibility ? robust operation over the installed base of category-5 (cat-5) twisted pair cabling state-of-the-art dsp architecture implements digital adaptive equalization, echo cancellation, and cross-talk cancellation ? robust performance in noisy environments ? tolerance of common electrical signal impairments phy cable correction and diagnostics ? improved end-user troubleshooting ? tolerance of common wiring faults ? low-power link-up (lplu) ?smart speed ? smart power-down ? enables link in low-power mode ? reacts to various link speeds features benefits transmit and receive ip, tcp and udp checksum off- loading capabilities ? lower cpu utilization transmit tcp segmentation ? increased throughput and lower cpu utilization ? large send offload feature (in microsoft* windows* xp) compatible ipv6 offloading ? checksum and segmentation capability extended to new standard packet type advanced packet filtering ? 16 exact matched packets (unicast or multicast) ? 4096-bit hash filter for multicast frames ? promiscuous (unicast and multicast) transfer mode support ? optional filtering of invalid frames ieee 802.1q vlan support with vlan tag insertion, stripping and packet filtering for up to 4096 vlan tags ? ability to create multiple virtual lan segments descriptor ring management hardware for transmit and receive ? optimized fetching and write-back mechanisms for efficient system memory and pci bandwidth usage 9 kb jumbo frame support ? high throughput for large da ta transfers on networks supporting jumbo frames
product datasheet 7 82571EB/82572ei gigabit ethernet controller 2.5 manageability features 2.6 additional device features features benefits manageability features: ? two smbus ports one with fast management link capability ? alerting standards format 1.0 and 2.0 ? advanced power management (wake on lan) ? alerting and control via standardized interfaces ? network management flexibility ? manageability data transfers up to 8 mb/s peak rate on-board microcontroller ? enables effective asf 2.0 implementations ? promotes customized designs ? allows packets routing to and from either lan port and a server management processor ? supports serial text an d keyboard redirection ? supports remote floppy/cd preboot execution environment (pxe) flash interface support (32-bit nd 64-bit) ? local flash interface for pxe image compliance with pci power management 1.1 and acpi 2.0 register set compliant including: ? d0 and d3 power states ? network device class power management specification 1.1 ? pci power management capability requirements for pc and embedded applications snmp and rmon statistic counters ? easy system monitoring with industry standard consoles sdg 3.0, wfm 3.0, and pc2001 compliance ? remote network management capabilities through dmi 2.0 and snmp software wake on lan support ? packet recognition and wake-up for nic and lom applications without software configuration features benefits 82571EB: two complete gigabit ethernet connections in a single device ? inherent dual port teaming ability ? high availability using one port for failover ? higher throughput than single gigabit ethernet port ? lower latency due to one electrical load on the bus ? saves critical board space ? reduced multi-port gigabit ethernet costs integrated serdes ? supports backplane and fiber applications as well as copper-based gigabit four activity and link indicatio n outputs (per port) that directly drive leds ? link and activity indications (10, 100, and 1000 mbps) on each port programmable led functionality ? software definable function (speed, link, and activity) and blinking allowing fl exible led implementations internal pll for clock generation can use a 25 mh z crystal ? lower component count and system cost
82571EB/82572 gigabit ethernet controller 8 product datasheet 2.7 technology features jtag (ieee 1149.1) test access port built in silicon ? simplified testin g using boundary scan four software definable pins per port ? additional flexibility for le ds or other low speed i/o devices provides loopback capabilities ? validates silicon integrity features benefits 256-pin flip-chip ball grid array (fc-bga) package ? 17 mm x 17 mm component occupies only 28% more board space than a single port device implemented in 90 nm cmos process ? offers lowest geometry to minimize power and size while maintaining intel quality and reliability standards operating temperature: 1000base-t, 0 c to 55 c (with thermal management) 1000base-t, 0 c to 70 c (with increased thermal management) 1000base-sx/lx (or serdes backplane), 0 c to 70 c storage temperature 65 c to 140 c ? simple thermal design typical targeted power dissipation: ~3.50 w @ d0 1000 mbps ~0.78mw @ d3 100 mbps (wakeup enabled) ~0.36mw @ d3 wakeup disabled ? minimizes impact of incorporating gigabit instead of fast ethernet. features benefits
product datasheet 9 82571EB/82572ei gigabit ethernet controller 3.0 signal descriptions note: the targeted signal names are subject to change w ithout notice. verify with your local intel sales office that you have the latest information before finalizing a design. 3.1 signal type definitions the signals of the 82571EB/82572ei controller are electrically defined as follows: 3.2 pci express interface name definition i input. standard input only digital signal. o output. standard output only digital signal. ts tri-state. bi-directional three-state di gital input/output signal. od open drain. wired-or with other agents. the signaling agent asserts the od signal, but the sign al is returned to the in active state by a weak pull- up resistor. the pull-up resistor may require two or three clock periods to fully restore the signal to the de-asserted state. a analog. pci express*, serdes, or, phy analog signal. a(i) analog-input. standard input only analog signal. a(o) analog-output. standard output only analog signal. p power. power connection, voltage reference, or other reference connection. symbol type name and function pern[3:0] perp[3:0] a(i) high speed serial receive data. these signals connect to corresponding petn and petp signals on a system motherboard or a pci express connector. series ac coupling capacitors are required at th e transmitter end. the pci expr ess differential inputs are clocked at 2.5 gb/s. petn[3:0] petp[3:0] a(o) high speed serial transmit data. these signals connect to corresponding pern and perp signals on a system motherboard or a pci express connector. series ac coupling capacitors are required at the 82571EB/ 82572ei controller end. the pci express differential outputs are clocked at 2.5 gb/s. pe_rcompp pe_rcompn p high speed serial impedance compensation. connect the recommen ded resistor value across these balls. refer to the 82571EB/82572ei design guide for the recommended value. pe_clkp pe_clkn i 100 mhz differential clock for the pci express interface. the reference clock is furnished by the system and has a 300 ppm frequency tolerance. pe_rstn i pci express reset. when the signal is low, all pci expr ess functions are held in reset. when the signal is high, it denotes that ma in power is available to the 82571EB/82572ei controller and the reference clock is running. in systems with a pci express add-in card, this signal routes to the connector.
82571EB/82572ei gigabit ethernet controller 10 product datasheet 3.3 power management signals 3.4 smb and fast manage ment link bus signals symbol type name and function aux_pwr i auxiliary power present. if the auxiliary power signal is high, then auxiliary power is present and the 82571EB/82572ei device should support the d3 cold power state. lan0_dis_n lan1_dis_n/ rsvd_b8 i lan disables 0 and 1. disables individual ethernet ports. state is latched upon a rising edge of perst_n or a pci express rese t event. this pin has an internal pull-up resistor. dev_off_n i device off. asynchronously disables ethernet co ntroller, including voltage regulator control outputs if selected in ctrl_ext. this pin has an internal pull-up resistor. pe_waken od wake. the 82571EB/82572ei device dr ives this signal low wh en it receives a wake-up event and either the pme enab le bit in the power manageme nt control/status register or the advanced power management enable (apme) bit of the wake-up control register (wuc) is 1b. symbol type name and function smbclk0/flbmck smbclk1 i/o smb clock. the smb clock signals are open dr ain signals for the serial smb interface (ports a and b). alternatively, wh en smb port a is configured for a fast management link bus, smb clock a b ecomes the fast management link bus master clock. the fast management li nk bus can be clocked up to 6.5 mhz. smbd0/flbmd smbd1 i/o smb data. the smb data signals are open drain signals for the serial smb interface (ports a and b). alternatively, when smb port a is configured for a fast management link bus, smb data a beco mes fast management link bus master data. smbalrt_n/ pci_pwr_good i/o smb alert. the smb alert signal is an open drain signal for serial smb port a. in asf mode, this signal acts as a power good in put. it acts as an alert input in 82559 compatible mode. flbsd o fast management link bus slave data. when smb port a is configured for a fast management link bus, this signal becomes the serial data path for slave data from the 82571EB/82572ei controller. flbintex o fast management link bus interrupt extension. driven by the 82571EB/ 82572ei controller as a slave to alert the mast er to read data. alte rnatively, it signals the master to extend the low phase of the clock.
product datasheet 11 82571EB/82572ei gigabit ethernet controller 3.5 eeprom and serial fl ash interface signals 3.6 led signals symbol type name and function ee_di o eeprom data input. the eeprom data input pin is used for output to the spi eeprom memory device. ee_do i eeprom data output. the eeprom data output pin is used for input from the spi eeprom memory device. the ee_do includes an internal pull-up resistor. ee_cs_n o eeprom chip select. the eeprom chip select signal is used to enable the device. ee_sk o eeprom serial clock. the eeprom shift clock provides the clock rate for the spi eeprom interface, which is approximately 2 mhz. flsh_ce_n o flash chip enable output. used to enable flash device. flsh_sck o flash serial clock output . flsh_si o flash serial data input. this pin is an output to the memory device. flsh_so i flash serial data output. this pin is an input from the memory device. symbol type name and function led0_0 o led0_0. programmable led output for port a. as the link led, it indicates link connectivity on port a. led0_1 o led0_1. programmable led output for port a. as the activity led, it flashes to indicate receive activity on port a for packets destined for this node. led0_2 o led0_2. programmable led output fo r port a. as the link 100 led, it indicates link at 100 mbps for port a. led0_3 o led0_3. programmable led output for port a. as the link 1000 led, it indicates link at 1000 mbps for port a. led1_0/ rsvd_p8 o ledb0_n. programmable led output for port b. as the link led, it indicates link connectivity on port b. (82571 eb only.) led1_1/ rsvd_r8 o led1_1. programmable led output for port b. as the activity led, it flashes to indicate receive activity on port b for packets destined for this node. (82571 eb only.) led1_2/ rsvd_t8 o led1_2. programmable led output for port b. as the link 100 led, it indicates link at 100 mbps for port b. (82571 eb only.) led1_3/ rsvd_p9 o led1_3. programmable led output for port b. as the link 1000 led, it indicates link at 1000 mbps for port b. (82571 eb only.)
82571EB/82572ei gigabit ethernet controller 12 product datasheet 3.7 other signals 3.8 crystal signals 3.9 phy analog signals port 0 symbol type name and function sdp0_1 sdp0_2 sdp0_3 sdp0_4 sdp1_1/rsvd_p6 sdp1_2/rsvd_b6 sdp1_3/rsvd_c6 sdp1_4/rsvd_r6 ts software defined pin. the software defined pins are programmable w ith respect to input and output capability. sdp0_3 and sd p1_3 may optionally be configured as interrupt inputs. sdp signals default to inputs upon power-up, but may be configured differently by the eeprom. symbol type name and function xtal1 i crystal one. the crystal one pin is a 25 mhz input signal. it should be connected to a parallel resonant crystal with a frequency tolerance of 30 ppm or better. the other end of the crystal should be connected to xtal2. optionally, an os cillator can be connected to xtal 1. see the design guide for more information.. xtal2 o crystal two. crystal two is the output of an internal oscillator circuit used to drive a crystal into oscillation. symbol type name and function rbias0p rbias0n p bias resistors. these are the reference connections for the media dependent interface. the recommended resistor value should be connected across the po sitive/negative pair, even if the mdi interface is not used. re fer to the 82571EB/82572ei design guide for the recommended value. mdi_plus0_0 mdi_minus0_0 a media dependent interface [0]. 1000base-t : in mdi configuration, these correspond to bi_da+/-, and in mdi-x configuration, they co rrespond to bi_db+/-. 100base-tx : in mdi configuration, these are used for the transmit pair, and in mdi-x configuration, they are us ed for the receive pair. 10base-t : in mdi configuration, they are used for the transmit pair, and in mdi-x configuration, used for the receive pair.
product datasheet 13 82571EB/82572ei gigabit ethernet controller port 1 (82571EB only) mdi_plus0_1 mdi_minus0_1 a media dependent interface [1]. 1000base-t : in mdi configuration, these correspond to bi_db+/-, and in mdi-x configuration, they correspond to bi_da+/-. 100base-tx : in mdi configuration, they are used for the receive pair, and in mdi-x configuration, they are us ed for the transit pair. 10base-t : in mdi configuration, they are used for the receive pair, and in mdi-x configuration, they are us ed for the transit pair. mdi_plus0_2 mdi_minus0_2 a media dependent interface [2]. 1000base-t : in mdi configuration, these correspond to bi_dc+/-, and in mdi-x configuration, they correspond to bi_dd+/-. 100base-tx : unused. 10base-t : unused. mdi_plus0_3 mdi_minus0_3 a media dependent interface [3]. 1000base-t : in mdi configuration, these correspond to bi_dd+/-, and in mdi-x configuration, they correspond to bi_dc+/-. 100base-tx : unused. 10base-t : unused. symbol type name and function symbol type name and function rbias1p/ rsvd_m14 rbias1n/ rsvd_n14 p bias resistors. these are the reference connections for the media dependent interface. the recommended resistor value should be co nnected across the positive/negative pair, even if the mdi interface is not used. refer to the 82571EB/82572ei design guide for the recommended value. mdi_plus1_0/ rsvd_t14 mdi_minus1_0/ rsvd_r14 a media dependent interface [0]. 1000base-t : in mdi configuration, these correspond to bi_da+/-, and in mdi-x configuration, they correspond to bi_db+/-. 100base-tx : in mdi configuration, they are used for the transmit pair, and in mdi-x configuration, they are used for the receive pair. 10base-t : in mdi configuration, they are used for the transmit pair, and in mdi-x configuration, they are used for the receive pair. mdi_plus1_1/ rsvd_t15 mdi_minus1_1/ rsvd_r15 a media dependent interface [1]. 1000base-t : in mdi configuration, these correspond to bi_db+/-, and in mdi-x configuration, they correspond to bi_da+/-. 100base-tx : in mdi configuration, they are used for the receive pair, and in mdi-x configuration, they are us ed for the transit pair. 10base-t : in mdi configuration, they are used for the receive pair, and in mdi-x configuration, they are us ed for the transit pair. mdi_plus1_2/ rsvd_p16 mdi_minus1_2/ rsvd_p15 a media dependent interface [2]. 1000base-t : in mdi configuration, these correspond to bi_dc+/-, and in mdi-x configuration, they correspond to bi_dd+/-. 100base-tx : unused. 10base-t : unused. mdi_plus1_3/ rsvd_n16 mdi_minus1_3/ rsvd_n15 a media dependent interface [3]. 1000base-t : in mdi configuration, these correspond to bi_dd+/-, and in mdi-x configuration, they correspond to bi_dc+/-. 100base-tx : unused. 10base-t : unused.
82571EB/82572ei gigabit ethernet controller 14 product datasheet 3.10 serializer / deserializer signals 3.11 test interface signals symbol type name and function srdsi_0_plus srdsi_0_minus srdsi_1_plus/ rsvd_m16 srdsi_1_minus/ rsvd_l16 a(i) serdes receive pairs. signals srdsi_0_plus and srdsi_0_minus make the differential receive pair for the 1.25 ghz se rial interface for port 0. for serializer/ deserializer operation, the inputs should be coupled to ecl voltage levels. signals srdsi_1_plus and srdsi_1_minus make the differential receive pair for the 1.25 ghz serial interface for port 1. for serializer/deserializer operation, the inputs should be coupled to ecl voltage levels. if the serdes interface is not used, these pins should not be connected. srdso_0_plus srdso_0_minus srdso_1_plus/ rsvd_k15 srdso_1_minus /rsvd_l15 a(o) serdes transmit pairs. signals srdso_0_plus and srdso_0_minus make the differential transmit pair for the 1.25 ghz se rial interface for port 0. for serializer/ deserializer operation, the outputs drive the lvpecl voltage levels. signals srdso_1_plus and srdso_1_minus make the differential transmit pair for the 1.25 ghz serial interface for port 1. for serializer/deserializer operation, the outputs drive the lvpecl voltage levels. if the serdes interface is not used, these pins should not be connected. srdsa_sig_det srdsb_sig_det/ rsvd_c4 i signal detects. these pins (srdsa_sig_det for port 0; srdsb_sig_det for port 1) indicate whether the serdes signals (co nnected to the 1.25 ghz serial interface) have been detected by the optical transceive rs. if the serdes interface is not used, the sig_det inputs can be left unconnected. srds_rcompp srds_rcompn a serdes impedance compensation. connect the recommended resistor value across these balls, even if not using the serdes interface. refer to the 82571EB/82572ei design guide for the recommended value. symbol type name and function jtck i jtag test access port clock. jtdi i jtag test access port test data in. jtdo o jtag test access port test data out. jtms i jtag test access port mode select.
product datasheet 15 82571EB/82572ei gigabit ethernet controller 3.12 power supply connections 3.12.1 digital and analog supplies 3.12.2 grounds, reserved pins and no connects ieee_test0p ieee_test0n ieee_test1p/ rsvd_r13 ieee_test1n/ rsvd_t13 o ieee analog test pins. differential outputs providing reference clocks for ieee phy conformance verification. for prototyp e testing, connect each pair to two-pin headers. for production systems, leave pins unconnected. therm_dp therm_dn o thermal diode reference. can be used to measur e the si temperature. test_en i factory test pin. attach a 1 k ? pull-down resistor to ground for normal operation. symbol type name and function vcc33 p 3.3v digital power supply. for i/o circuits. vcc18 p 1.8v analog power supply. for phy analog, phy i/o, pci express analog, and phase lock loop circuits, connect all 1.8v pins to a single power supply. vcc11 p 1.1v digital power supply. for core digital, phy digital, pci express digital and clock circuits, connect all 1.1v pins to a single power supply. symbol type name and function vssa p analog ground. connects to phy analog circuits. co nnect directly to analog ground. vss p digital ground. connects to core and digital i/o. connect to gnd. rsvd_ pin# p reserved pin. these pins are reserved by intel and may have factory test functions. for normal operation, do not connect any circuitry to thes e pins (allow them to ?float?). some special configurations may require pull-up or pull-down resistors on these pins. please refer to the 82571EB/82572ei design guide for more information. nc_pin# p no connect. this pin is not connected internally. symbol type name and function
82571EB/82572ei gigabit ethernet controller 16 product datasheet
product datasheet 17 82571EB/82572ei gigabit ethernet controller 4.0 voltage, temperature, and timing specifications 4.1 targeted absolute maximum ratings table 1. absolute maximum ratings a a. maximum ratings are refere nced to ground (vss). permanent devi ce damage is likely to occur if the ratings in this table are e xceeded for an indefinite duration. these values should not be used as the limits for normal device operations. symbol parameter min max unit vcc(3.3) dc supply voltage on 3.3v pins with respect to vss vss - 0.5 4.6 v vcc(1.8) dc supply voltage on 1.8v pins with respect to vss b b. during normal device power up and power down, the 1.8v and 1.1v supplies must not ramp before the 3.3v supply. vss - 0.3 2.5 v vcc(1.1) dc supply voltage on 1.1v pins with respect to vss b vss - 0.2 1.7 v v i / v o 3.3v i/o voltage 1.8v i/o voltage 1.1v i/o voltage vss - 0.5 vss - 0.3 vss - 0.2 4.6 2.5 1.7 v i o dc output current n/a 30 ma t storage storage temperature range -65 140 c esd per mil_std-883 test method 3015, specification 2001v latchup over/undershoot: 150 ma, 125 c n/a vdd overstress: vdd(3.3) * (7.2 v) v
82571EB/82572ei gigabit ethernet controller 18 product datasheet 4.2 targeted recommended operating conditions 4.2.1 general operating conditions table 2. recommended operating conditions a a. sustained operation of the device at conditions exceeding these va lues, even if they are within the absolute maximum rating l imits, might result in permanent damage. devi ce functionality to stated dc and ac limits is not guaranteed, if conditions exceed recommended oper- ating conditions. symbol parameter min max unit vcc(3.3) dc supply voltage on 3.3v pins 3.0 3.6 v vcc(1.8) dc supply voltage on 1.8v pins b, c b. see section 4.2.2 for voltage ramp and se quencing reco mmendations. c. operation with internal voltage regulator control of pnp pass transistor may exceed this range due to 82571EB process skew tr acking. 1.71 1.89 v vcc(1.1) dc supply voltage on 1.1v pins 1.045 1.155 v tr / tf input rise/fall time (normal input) 0 200 ns t a operating temperature range (ambient) 0 55 d d. 1000base-t designs require therma l management (heatsink and/or forced air flow) to achieve 0 to 55 c operation. increased t hermal management can increase this temperature range to 0 to 70 c. applications using the serdes interface are rated for 0 to 70 c without thermal management. c t j junction temperature n/a 110 c
product datasheet 19 82571EB/82572ei gigabit ethernet controller 4.2.2 voltage ramps table 3. 3.3v supply voltage ramp parameter description min max unit rise time time from 10% to 90% mark 0.1 100 a a. good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. ms monotonicity voltage dip allowed in ramp n/a 0 mv slope ramp rate at any time between 10% to 90% 24 28000 mv/ms operational range voltage range for normal operating conditions 33.6 v ripple maximum voltage ripple at a bandwidth equal to 50 mhz n/a 70 mv peak-peak overshoot settling time overshoot time upon ramp b b. excessive overshoot can affect long term reliability. n/a 0.05 ms overshoot maximum voltage allowed b n/a 100 mv table 4. 1.8v supply voltage ramp parameter description min max unit rise time time from 10% to 90% mark 0.1 100 a a. good design practices achieve voltage ramps to within the regulation bands in approximately 20 ms or less. ms monotonicity voltage dip allowed in ramp n/a 0 mv slope ramp rate at any time between 10% to 90% 14 60000 mv/ms operational range voltage range for normal operating conditions 1.71 1.89 v ripple maximum voltage ripple at a bandwidth equal to 1 mhz n/a 40 mv peak-peak overshoot settlingtime overshoot time upon ramp b b. excessive overshoot can affect long term reliability. n/a 0.1 ms overshoot maximum voltage allowed b n/a 100 mv table 5. 1.1v supply voltage ramp parameter description min max unit rise time time from 10% to 90% mark 0.1 100 a ms monotonicity voltage dip allowed in ramp n/a 0 mv slope ramp rate at any time between 10% to 90% 7.6 33600 mv/ms operational range voltage range for normal operating conditions 1.045 1.155 v
82571EB/82572ei gigabit ethernet controller 20 product datasheet 4.2.3 voltage power sequencing options to meet 375 ma inrush current requirements (not including external cap acitors) the ramp time should be 5 ms -100 ms on all power rails. for faster ramps (100 us - 5 ms), expect higher inrush current due to the high charging current of the d ecoupling capacitors of 3.3v, 1.8v and 1.1v rails. 4.3 dc specifications ripple maximum voltage ripple at a bandwidth equal to 1 mhz n/a 40 mv peak-peak overshoot settlingtime overshoot time upon ramp b n/a 0.05 ms overshoot maximum voltage allowed b n/a 100 mv a. good design practices achieve voltage ramps to within the regulation bands in appr oximately 20 ms or less. b. excessive overshoot can affe ct long term reliability. table 5. 1.1v supply voltage ramp table 6. dc characteristics symbol parameter condition min typ max units vcc(3.3) dc supply voltage on 3.3v pins 3.00 3.30 3.60 v vcc(1.8) dc supply voltage on 1.8v pins 1.71 1.80 1.89 v vcc(1.1) dc supply voltage on 1.1v pins 1.045 1.100 1.155 v
product datasheet 21 82571EB/82572ei gigabit ethernet controller 4.3.4 power specifications--82571EB table 7. d0a--active link d0a--active link @10 mbps @100 mbps @ 1000 mbps (copper) @ 1000 mbps (serdes) typ icc (ma) a a. typical conditions: operating temperature (t a ) = 25 c, nominal voltages and contin- uous network traffic at link speed at full duplex. typ icc (ma) a typ icc (ma) a max icc (ma) a typ icc (ma) a max icc (ma) b b. maximum conditions: maximum operating temperature (t j ) values, typical voltage values and continuous network traffic at link speed at full duplex. 3.3v 26 26 26 34 42 46 1.8v 350 399 893 913 254 282 1.1v 370 456 1022 1520 529 1002 total device power 1.12w 1.31w 2.82w 3.43w 1.18w 1.76w
82571EB/82572ei gigabit ethernet controller 22 product datasheet table 8. d0a--idle link l0s only d0a--idle link l0s only unplugged--no link @10mbps @100mbps @1000mbps (copper) typ icc (ma) a a. typical conditions: room temperature (ta)=25c, nominal voltages and idle network (no traffic) at full du- plex 3.3v 26 26 26 26 1.8v 130 123 306 837 1.1v 332 334 414 839 total device power 0.69w 0.67w 1.10w 2.52w table 9. d3cold d3cold - wake-up enabled d3cold- wake disabled (no link) @10 mbps @100 mbps typ icc (ma) a, b a. d3 cold activated on a windows server 2003 os--using hbernate mode b. l0s enable, l1 disabled typ icc (ma) a, b typ icc (ma) a b 3.3v 26 26 26 1.8v 74 243 76 1.1v 133 236 123 total device power 0.37w 0.78w 0.36w
product datasheet 23 82571EB/82572ei gigabit ethernet controller 4.3.5 power specifica tions--82572ei ta bl e 10 . d(r) unintialized d(r) uninitialized disabled through lan_dis_n typ icc (ma) disabled through dev_off_n typ icc (ma) 3.3v 26 26 1.8v 63 68 1.1v 130 83 total d evic e power 0.34w 0.30w table 11. d0a--active link d0a--active link @10 mbps @100 mbps @ 1000 mbps (copper) typ icc (ma) a a. typical conditions: operating temperature (t a ) = 25 c, nominal voltages and continuous network traffic at link speed at full duplex. typ icc (ma) a typ icc (ma) a max icc (ma) a 3.3v 26 26 26 34 1.8v 210 211 484 502 1.1v 291 232 494 1023 total device power 0.78w 0.72w 1.50w 2.14w
82571EB/82572ei gigabit ethernet controller 24 product datasheet table 12. d0a--idle link d0a--idle link l0s only unplugged--no link @10mbps @100mbps @1000mbps (copper) typ icc (ma) a a. typical conditions: room temperature (ta)=25c, nomina l voltages and idle network (no traffic) at full du- plex 3.3v 26 26 26 26 1.8v 111 102 199 425 1.1v 176 179 218 839 total device power b b. los enabled; l1 disabled 0.48w 0.47w 0.68w 1.77w table 13. d3cold d3cold - wake-up enabled d3cold-wake disabled; unplugged, no link @10 mbps @100 mbps typ icc (ma) a, b a. d3 cold activated on a windows server 2003 os--using hbernate mode b. los enabled, l1 disabled typ icc (ma) a, b typ icc (ma) a b 3.3v 26 26 26 1.8v 77 173 84 1.1v 120 163 110 total device power 0.36w 0.58w 0.36w table 14. d(r) unintialized d(r) uninitialized disabled through lan_dis_n typ icc (ma) disabled through dev_off_n typ icc (ma) 3.3v 26 26
product datasheet 25 82571EB/82572ei gigabit ethernet controller 4.3.6 i/o characteristics 1.8v 60 68 1.1v 114 83 total d evic e power 0.32w 0.30w ta bl e 14 . d(r) unintialized d(r) uninitialized disabled through lan_dis_n typ icc (ma) disabled through dev_off_n typ icc (ma) table 15. i/o characteristics a symbol parameter condition min typ max units v ih input high voltage 2.0 n/a vcc(3.3) + 0.5 v v il input low voltage -0.5 n/a 0.8 v i in input current v in = vdd(3.3) or v ss -15 n/a 15 a v oh output high voltage i oh = -16 ma v cc = min 2.4 n/a n/a v i oh = -100 a v cc = min v cc - 0.02 n/a n/a v ol output low voltage i ol = 16 ma v cc = min n/a n/a 0.4 v i ol = 100 a v cc = min n/a n/a 0.2 i oz off-state output leakage current v o = v cc or v ss -10 n/a 10 a c in b input capacitance n/a 2.5 n/a pf pu internal pull-up 2.6 n/a 5.5 k ? a. the input buffer also has hysteresis > 160 mv. b. c in = 2.5 pf(maximum input capacitance), c out = 16 pf (characterized max output load capacitance per 160 mhz).
82571EB/82572ei gigabit ethernet controller 26 product datasheet 4.4 targeted ac characteristics table 16. 25 mhz clock input requirements symbol parameter min typ max unit f0 frequency n/a 25.000 n/a mhz df0 frequency variation -50 n/a +50 ppm dc duty cycle 40 n/a 60 % tr rise time n/a n/a 5 ns tf fall time n/a n/a 5 ns jptp clock jitter (peak-to-peak) a n/a n/a 250 ps c in input capacitance n/a 20 n/a pf t operating temperature n/a n/a 70 c aptp input clock amplitude (peak-to-peak) 1.0 1.2 1.3 v vcm clock common mode n/a 0.6 n/a v a. clock jitter is defined according to the recommendati ons of part 40.6.1.2.5 ieee 1000base-t standard (at least 10 5 clock edges, filtered by hpf with cut off frequency of 5000 hz).
product datasheet 27 82571EB/82572ei gigabit ethernet controller table 17. reference crystal specification requirements specification value vibrational mode fundamental nominal frequency 25.000 mhz at 25 c frequency tolerance ? 30 ppm recommended ? 50 ppm across the entire operating temperature range (required by ieee specifications) temperature stability +/- 30 ppm at 0 c to 70 c calibration mode parallel load capacitance 20 pf to 24 pf shunt capacitance 6 pf maximum series resistance, rs 50 ? maximum drive level 0.5 mw maximum aging +/- 5.0 ppm per year maximum insulation resistance 500 ? minimum at dc 100 v board capacitance 4 pf external capacitors 27 pf board resistance 0.1 ? table 18. link interface clock requirements symbol parameter min typ max unit fgtx a gtx_clk frequency n/a 125 n/a mhz a. gtx_clk is used externally for test purposes only. table 19. eeprom interface clock requirements symbol parameter min typ max unit fsk spi eeprom clock n/a 2 2.1 mhz table 20. ac test loads for general output pins symbol parameter min typ max unit c l capacitance of test load n/a 16 n/a pf
82571EB/82572ei gigabit ethernet controller 28 product datasheet figure 2. ac test load s for general output pins 4.5 targeted timing specifications note: timing specifications are prelimin ary and subject to change. verify with your local intel sales office that you have the latest info rmation before fina lizing a design. 4.5.1 pci express interface 4.5.1.1 differential transmitter (tx) output specifications c l table 21. differential transmit ter (tx) output specifications symbol parameter min typ max units ui unit interval 399.88 400 400.12 ps v tx-diffp-p differential peak to peak output voltage 0.800 n/a 1.2 v v tx-de-ratio de-emphasized differential output voltage (ratio) -3.0 -3.5 -4.0 db t tx-eye minimum tx eye width 0.70 n/a n/a ui t tx-rise, t tx-fall d+/d- tx output rise/fall time 0.125 n/a n/a ui v tx-cm-acp rms ac peak common mode output voltage n/a n/a 20 mv v tx-cm-dc-line- delta absolute delta of dc common mode voltage between d+ and d- 0n/a25mv v tx-idle-diffp electrical idle differential peak output voltage 0n/a20mv
product datasheet 29 82571EB/82572ei gigabit ethernet controller figure 3. pci express transmitter eye diagram v tx-rcv-detect the amount of voltage change allowed during receiver detectoin n/a n/a 600 mv rl tx-diff differential return loss 12 n/a n/a db rl tx-cm common mode return loss 6n/an/adb z tx-diff-dc dc differential tx impedance 80 100 120 ? l tx-skew lane-tolane output skew n/a n/a 500 + 2 ui ps table 21. differential transmit ter (tx) output specifications symbol parameter min typ max units [de-emphasized bit] 566 mv (3 db) >= v tx-diffp-p-min >= 505 mv (4 db) [transition bit] v tx-diffp-p-min = 800 mv v tx-diff = 0 mv (d+ d- crossing point) [transition bit] v tx-diffp-p-min = 800 mv 0.7 ui = ui - 0.3 ui(j tx-total-max ) v tx-diff = 0 mv (d+ d- crossing point)
82571EB/82572ei gigabit ethernet controller 30 product datasheet figure 4. pci express transmitter test load 4.5.1.2 differential receiver (rx) input specifications tx silicon + package c = c tx c = c tx r = 50 ? r = 50 ? d+ package pin d- package pin table 22. differential receiv er (rx) output specifications symbol parameter min typ max units ui unit interval 399.88 400 400.12 ps v rx-diffp-p differential peak to peak output voltage 0.175 n/a 1.2 v r tx-eye minimum rx eye width 0.4 n/a n/a ui v rx-cm-acp ac peak common mode input voltage n/a n/a 150 mv rl rx-diff differential return loss 15 n/a n/a db rl rx-cm common mode return loss 6n/an/adb z rx-diff-dc dc differential input impedance 80 100 120 ? l rx-skew total skew n/a n/a 20 ns
product datasheet 31 82571EB/82572ei gigabit ethernet controller figure 5. pci express receiver eye diagram 4.5.2 eeprom interface v rx-diffp-p-min > 175 mv v rx-diff = 0 mv (d+ d- crossing point) 0.4 ui = t rx-eye-min v rx-diff = 0 mv (d+ d- crossing point) table 23. eeprom interfa ce time specifications symbol parameter min typ max units t sck sck clock frequency 022.1mhz t ri input rise time n/a 2.5 ns 2 s t fi input fall time n/a 2.5 ns 2 s t wh sck high time a 200 250 n/a ns t wh sck low time a 200 250 n/a ns t cs cs high time 250 n/a n/a ns t css cs setup time 250 n/a n/a ns t csh cs hold time 250 n/a n/a ns t su data-in setup time 50 n/a n/a ns t h data-in hold time 50 n/a n/a ns t v output valid 0 n/a 200 ns t ho output hold time 0 n/a n/a ns t dis output disable time n/a n/a 250 ns t wc write cycle time n/a n/a 10 ms a. 50% duty cycle.
82571EB/82572ei gigabit ethernet controller 32 product datasheet figure 6. eeprom interface time diagram cs sck si so v ih v il v ih v il v ih v il v ih v il t css t csh t cs t wh t wl t su t h t v t ho t dio hi-z hi-z valid in
product datasheet 33 82571EB/82572ei gigabit ethernet controller 4.5.3 flash interface figure 7. flash int erface time diagram table 24. flash interface time specifications symbol parameter min typ max units t sck sck clock frequency 0 15.625 20 mhz t ri input rise time n/a 2.5 ns 20 ns t fi input fall time n/a 2.5 ns 20 ns t wh sck high time a a. 50% duty cycle. 20 32 n/a ns t wh sck low time a 20 32 n/a ns t cs cs high time 25 n/a n/a ns t css cs setup time 25 n/a n/a ns t csh cs hold time 250 n/a n/a ns t su data-in setup time 5n/an/ans t h data-in hold time 5 n/a n/a ns t v output valid 0 n/a 20 ns t ho output hold time 0 n/a n/a ns t dis output disable time n/a n/a 100 ns t ec erase cycle time per sector n/a 60 100 s cs vih vil vih vil vih vil tcss twh twl tcsh tcs sck valid in tsu th si voh vol hi-z hi-z tho tdis so tv
82571EB/82572ei gigabit ethernet controller 34 product datasheet
product datasheet 33 82571EB/82572ei gigabit ethernet controller 5.0 package and pinout information this section describes the 82571EB/82572ei device physical characteristics. the pin number-to- signal mapping is indicated beginning with table 25 . note: the targeted signal names are subject to change w ithout notice. verify with your local intel sales office that you have the latest information before finalizing a design. 5.1 package information the 82571EB/82572ei device is a 256-lead flip-chi p ball grid array (fc-bga) measuring 17 mm by 17 mm. the nominal ball pitch is 1 mm. see figure 9 . figure 8. 82571EB/82572ei controller fc-bga package ball pad dimensions 0.43 mm solder resist opening 0.62 mm metal diameter detail area
82571EB/82572ei gigabit ethernet controller 34 product datasheet figure 9. 82571EB/ 82572ei mechanical specifications
product datasheet 35 82571EB/82572ei gigabit ethernet controller 5.2 thermal specification the 82571EB/82572ei device is specified for operation when the am bient temperature (t a ) is within the range of 0 c to 55 c. for more information about th e thermal characteristics of the device, including operation outside of this range, please refer to the 82571EB/82572eb thermal application note, ap-490 5.3 pinout information signal names apply to both the 82571EB and the 82572ei unless there is a ?/?, which indicates that the the first name is for the 82571EB and the second name is for the 82572ei. table 25. pci express signals signal pin signal pin signal pin pern0 r2 pern3 b1 petn2 d2 perp0t2perp3c1petp2e2 pern1 m2 petn0 p1 petn3 a2 perp1 n2 petp0 r1 petp3 b2 pern2 e1 petn1 l1 pe_rcompn g2 perp2 f1 petp1 m1 pe_rcompp h2 pe_clkn j2 pe_clkp k2 pe_rstn t6 table 26. power management signals signal pin signal pin lan0_dis_n b7 pe_waken p11 lan1_dis_n/ rsvd_b8 b8 aux_pwr c8 dev_off_n t3 table 27. smb/fast management link bus signals signal pin signal pin signal pin smbclk0/ flbmck t12 smbclk1 p13 smbalrt_n/ pci_pwr_good r11 smbd0/flbmd r12 smbd1 p12 flbsd p7 flbintex r7
82571EB/82572ei gigabit ethernet controller 36 product datasheet table 31. phy and serdes signals table 28. eeprom and serial flash interface signals signal pin signal pin signal pin ee_sk b12 ee_cs_n c13 flsh_si t9 ee_do a12 flsh_sck r10 flsh_so r9 ee_di c12 flsh_ce_n p10 table 29. led signals signal pin signal pin signal pin led0_0 b11 led0_1 c11 led1_3/rsvd_p9 p9 led0_2 b10 led1_0/rsvd_p8 p8 led1_1/rsvd_r8 r8 led0_3 c10 led1_2/rsvd_t8 t8 table 30. other signals signal pin signal pin sdp0_0 b9 sdp1_0/rsvd_p6 p6 sdp0_1 a9 sdp1_1/rsvd_b6 b6 sdp0_2 c9 sdp1_2/rsvd_c6 c6 sdp0_3 a8 sdp1_3/rsvd_r6 r6 signal pin signal pin signal pin mdi_minus0_0 b14 mdi_minus1_3/ rsvd_n15 n15 srdsi_0_minus f16 mdi_plus0_0 a14 mdi_plus1_3/ rsvd_n16 n16 srdsi_0_plus e16 mdi_minus0_1 b15 rbias0n d14 srdso_1_minus/ rsvd_l15 l15 mdi_plus0_1 a15 rbias0p e14 srdso_1_plus/ rsvd_k15 k15 mdi_minus0_2 c15 rbias1n/ rsvd_n14 n14 srdsb_sig_det/ rsvd_c4 c4 mdi_plus0_2 c16 rbias1p/ rsvd_m14 m14 srdsi_1_minus/ rsvd_l16 l16 mdi_minus0_3 d15 srdso_0_minus f15 srdsi_1_plus/ rsvd_m16 m16 mdi_plus1_2/ rsvd_p16 p16 srdso_0_plus g15 srdsa_sig_det b4
product datasheet 37 82571EB/82572ei gigabit ethernet controller mdi_plus0_3 d16 mdi_minus1_0/ rsvd_r14 r14 srds_rcompn h14 mdi_plus1_1/ rsvd_t15 t15 mdi_plus1_0/ rsvd_t14 t14 srds_rcompp h15 mdi_minus1_2/ rsvd_p15 p15 mdi_minus1_1/ rsvd_r15 r15 table 32. test interface signals signal pin signal pin signal pin jtck p4 ieee_test0n a13 therm_dp d4 jtdi r3 ieee_test0p b13 therm_dn d5 jtdo p5 ieee_test1n/ rsvd_t13 t13 jtms p3 ieee_test1p/ rsvd_r13 r13 test_en r5 table 33. crystal signals signal pin xtal1 j16 xtal2 h16 signal pin signal pin signal pin
82571EB/82572ei gigabit ethernet controller 38 product datasheet table 34. power signals signal pin signal pin signal pin vcc33 a4 vcc18 m4 vcc11 m9 vcc33 a10 vcc18 m5 vcc11 m13 vcc33 d7 vcc18 k4 vcc11 e12 vcc33 d9 vcc11 e7 vcc11 f13 vcc33 n7 vcc11 e9 vcc11 g12 vcc33 n9 vcc11 e13 vcc11 k12 vcc33 t5 vcc11 f7 vcc11 l13 vcc33 t11 vcc11 f9 vcc11 m12 vcc18 e10 vcc11 g7 vcc11 f12 vcc18 f10 vcc11 g9 vcc11 l12 vcc18 g10 vcc11 h7 vcc11 j4 vcc18 h10 vcc11 h9 vcc11 j5 vcc18 j10 vcc11 j7 vcc11 n4 vcc18 k10 vcc11 j9 vcc11 n5 vcc18 l10 vcc11 k7 vcc18 m10 vcc11 k9 vcc18 h4 vcc11 l7 vcc18 h5 vcc11 l9 vcc18 k5 vcc11 m7
product datasheet 39 82571EB/82572ei gigabit ethernet controller table 35. ground signals signal pin signal pin signal pin vssa a1 vssa h13 vss a5 vssa a16 vssa j3 vss a11 vssa b16 vssa j11 vss d6 vssa c2 vssa j12 vss d8 vssa c14 vssa j13 vss d10 vssa d1 vssa k1 vss e5 vssa d3 vssa k3 vss e6 vssa d11 vssa k11 vss e8 vssa d12 vssa k13 vss f5 vssa d13 vssa k14 vss f6 vssa e3 vssa k16 vss f8 vssa e4 vssa l2 vss g6 vssa e11 vssa l3 vss g8 vssa e15 vssa l4 vss h6 vssa f2 vssa l5 vss h8 vssa f3 vssa l11 vss j6 vssa f4 vssa l14 vss j8 vssa f11 vssa m3 vss k6 vssa f14 vssa m11 vss k8 vssa g1 vssa m15 vss l6 vssa g3 vssa n1 vss l8 vssa g4 vssa n3 vss m6 vssa g5 vssa n11 vss m8 vssa g11 vssa n12 vss n6 vssa g13 vssa n13 vss n8 vssa g14 vssa p2 vss n10 vssa g16 vssa p14 vss t4 vssa h3 vssa r16 vss t10 vssa h11 vssa t1 vssa h12 vssa t16
82571EB/82572ei gigabit ethernet controller 40 product datasheet table 36. reserved and no connect signals note: these pins are reserved by intel and may have factory test fu nctions. for normal operation, do not connect any circuitry to these pins (allow them to ?float?). some configurations may require pull-up or pull-down resistors on these pins. please refer to the 82571EB/82572ei design guide for more information. signal pin rsvd_a3 a3 rsvd_ a6 a6 device_dis_n a7 rsvd_b3 b3 rsvd_ b5 b5 rsvd_ c3 c3 rsvd_ c5 c5 rsvd_ c7 c7 rsvd_h1 h1 rsvd_j1 j1 rsvd_j14 j14 rsvd_j15 j15 lan_pwr_good r4 nc_t7 t7 table 37. signal names in pin order (sheet 1 of 8) signal name pin vssa a1 petn3 a2 rsvd_a3 a3 vcc33 a4 vss a5 rsvd_a6 a6 device_dis_n a7 sdp0_3 a8 sdp0_1 a9 vcc33 a10 vss a11 ee_do a12 ieee_test0n a13 mdi_plus0_0 a14 mdi_plus0_1 a15 vssa a16
product datasheet 41 82571EB/82572ei gigabit ethernet controller pern3 b1 petp3 b2 rsvd_b3 b3 srdsa_sig_det b4 rsvd_b5 b5 sdp1_1/rsvd_b6 b6 lan0_dis_n b7 lan1_dis_n/rsvd_b8 b8 sdp0_0 b9 led0_2 b10 led0_0 b11 ee_sk b12 ieee_test0p b13 mdi_minus0_0 b14 mdi_minus0_1 b15 vssa b16 perp3 c1 vssa c2 rsvd_c3 c3 srdsb_sig_det/rsvd_c4 c4 rsvd_c5 c5 sdp1_2/rsvd_c6 c6 rsvd_c7 c7 aux_pwr c8 sdp0_2 c9 led0_3 c10 led0_1 c11 ee_di c12 ee_cs_n c13 vssa c14 mdi_minus0_2 c15 mdi_plus0_2 c16 vssa d1 petn2 d2 vssa d3 therm_dp d4 therm_dn d5 vss d6 table 37. signal names in pin order (sheet 2 of 8) signal name pin
82571EB/82572ei gigabit ethernet controller 42 product datasheet vcc33 d7 vss d8 vcc33 d9 vss d10 vssa d11 vssa d12 vssa d13 rbias0n d14 mdi_minus0_3 d15 mdi_plus0_3 d16 pern2 e1 petp2 e2 vssa e3 vssa e4 vss e5 vss e6 vcc11 e7 vss e8 vcc11 e9 vcc18 e10 vssa e11 vcc11 e12 vcc11 e13 rbias0p e14 vssa e15 srdsi_0_plus e16 perp2 f1 vssa f2 vssa f3 vssa f4 vss f5 vss f6 vcc11 f7 vss f8 vcc11 f9 vcc18 f10 vssa f11 vcc11 f12 table 37. signal names in pin order (sheet 3 of 8) signal name pin
product datasheet 43 82571EB/82572ei gigabit ethernet controller vcc11 f13 vssa f14 srdso_0_minus f15 srdsi_0_minus f16 vssa g1 pe_rcompn g2 vssa g3 vssa g4 vssa g5 vss g6 vcc11 g7 vss g8 vcc11 g9 vcc18 g10 vssa g11 vcc11 g12 vssa g13 vssa g14 srdso_0_plus g15 vssa g16 rsvd_h1 h1 pe_rcompp h2 vssa h3 vcc18 h4 vcc18 h5 vss h6 vcc11 h7 vss h8 vcc11 h9 vcc18 h10 vssa h11 vssa h12 vssa h13 srds_rcompn h14 srds_rcompp h15 xtal2 h16 rsvd_j1 j1 pe_clkn j2 table 37. signal names in pin order (sheet 4 of 8) signal name pin
82571EB/82572ei gigabit ethernet controller 44 product datasheet vssa j3 vcc11 j4 vcc11 j5 vss j6 vcc11 j7 vss j8 vcc11 j9 vcc18 j10 vssa j11 vssa j12 vssa j13 rsvd_j14 j14 rsvd_j15 j15 xtal1 j16 vssa k1 pe_clkp k2 vssa k3 vcc18 k4 vcc18 k5 vss k6 vcc11 k7 vss k8 vcc11 k9 vcc18 k10 vssa k11 vcc11 k12 vssa k13 vssa k14 srdso_1_plus/rsvd_k15 k15 vssa k16 petn1 l1 vssa l2 vssa l3 vssa l4 vssa l5 vss l6 vcc11 l7 vss l8 table 37. signal names in pin order (sheet 5 of 8) signal name pin
product datasheet 45 82571EB/82572ei gigabit ethernet controller vcc11 l9 vcc18 l10 vssa l11 vcc11 l12 vcc11 l13 vssa l14 srdso_1_minus/rsvd_l15 l15 srdsi_1_minus/rsvd_l16 l16 petp1 m1 pern1 m2 vssa m3 vcc18 m4 vcc18 m5 vss m6 vcc11 m7 vss m8 vcc11 m9 vcc18 m10 vssa m11 vcc11 m12 vcc11 m13 rbias1p/rsvd_m14 m14 vssa m15 srdsi_1_plus/rsvd_m16 m16 vssa n1 perp1 n2 vssa n3 vcc11 n4 vcc11 n5 vss n6 vcc33 n7 vss n8 vcc33 n9 vss n10 vssa n11 vssa n12 vssa n13 rbias1n/rsvd_n14 n14 table 37. signal names in pin order (sheet 6 of 8) signal name pin
82571EB/82572ei gigabit ethernet controller 46 product datasheet mdi_minus1_3/rsvd_n15 n15 mdi_plus1_3/rsvd_n16 n16 petn0 p1 vssa p2 jtms p3 jtck p4 jtdo p5 sdp1_0/rsvd_p6 p6 flbsd p7 led1_0/rsvd_p8 p8 led1_3/rsvd_p9 p9 flsh_ce_n p10 pe_waken p11 smbd1 p12 smbclk1 p13 vssa p14 mdi_minus1_2/rsvd_p15 p15 mdi_plus1_2/rsvd_p16 p16 petp0 r1 pern0 r2 jtdi r3 lan_pwr_good r4 test_en r5 sdp1_3/rsvd_r6 r6 flbintex r7 led1_1/rsvd_r8 r8 flsh_so r9 flsh_sck r10 smbalrt_n/pci_pwr_good r11 smbd0/flbmd r12 ieee_test1p/rsvd_r13 r13 mdi_minus1_0/rsvd_r14 r14 mdi_minus1_1/rsvd_r15 r15 vssa r16 vssa t1 perp0 t2 dev_off_n t3 vss t4 table 37. signal names in pin order (sheet 7 of 8) signal name pin
product datasheet 47 82571EB/82572ei gigabit ethernet controller vcc33 t5 pe_rstn t6 nc_t7 t7 led1_2/rsvd_t8 t8 flsh_si t9 vss t10 vcc33 t11 smbclk0/flbmck t12 ieee_test1n/rsvd_t13 t13 mdi_plus1_0/rsvd_t14 t14 mdi_plus1_1/rsvd_t15 t15 vssa t16 table 37. signal names in pin order (sheet 8 of 8) signal name pin
82571EB/82572ei gigabit ethernet controller 48 product datasheet 5.4 visual pin assignments figure 10. 82571EB/82572ei visual pin assignment pt.1 (top view) abcdefgh 16 vssa vssa mdi_ plus0_2 mdi_ plus0_3 srdsi_0 _plus srdsi_0 _minus vssa xtal2 15 mdi_plus0_1 mdi_ minus0_1 mdi_ minus0_2 mdi_ minus0_3 vssa srdso_0 _minus srdso_0 _plus srds_rcompp 14 mdi_plus0_0 mdi_minus0_0 vssa rbias0n rbias0p vssa vssa srds_rcompn 13 ieee_test0n ieee_test0p ee_cs_n vssa vcc11 vcc11 vssa vssa 12 ee_do ee_sk ee_di vssa vcc11 vcc11 vcc11 vssa 11 vss led0_0 led0_1 vssa vssa vssa vssa vssa 10 vcc33 led0_2 led0_3 vss vcc18 vcc18 vcc18 vcc18 9 sdp0_1 sdp0_0 sdp0_2 vcc33 vcc11 vcc11 vcc11 vcc11 8 sdp0_3 lan1_dis_n/ rsvd_b8 aux_pwr vss vss vss vss vss 7 device_dis_n lan0_dis_n rsvd_c7 vcc33 vcc11 vcc11 vcc11 vcc11 6 rsvd_a6 sdp1_1/ rsvd_b6 sdp1_2/ rsvd_c6 vss vss vss vss vss 5 vss rsvd_b5 rsvd_c5 therm_ dn vss vss vssa vcc18 4 vcc33 srdsa_sig_det srdsb_sig_det/ rsvd_c4 therm_ dp vssa vssa vssa vcc18 3 rsvd_a3 rsvd_b3 rsvd_c3 vssa vssa vssa vssa vssa 2 petn3 petp3 vssa petn2 petp2 vssa pe_rcompn pe_rcompp 1 vssa pern3 perp3 vssa pern2 perp2 vssa rsvd_h1
product datasheet 49 82571EB/82572ei gigabit ethernet controller figure 11. 82571EB/82572ei visual pin assignment pt.2 (top view) jk l m n p r t xtal1 vssa srdsi_1_minus/ rsvd_l16 srdsi_1_plus/ rsvd_m16 mdi_plus1_3/ rsvd_n16 mdi_plus1_2/ rsvd_p16 vssa vssa 16 rsvd_j15 srdso_1_ plus/rsvd_k15 srdso_1_ minus/rsvd_l15 vssa mdi_minus1_3/ rsvd_n15 mdi_minus1_2 /rsvd_p15 mdi_minus1_1/ rsvd_15 mdi_plus1_1 /rsvd_t15 15 rsvd_j14 vssa vssa rbias1p/ rsvd_m14 rbias1n/ rsvd_n14 vssa mdi_minus1_0/ rsvd_r14 mdi_plus1_0 /rsvd_t14 14 vssa vssa vcc11 vcc11 vssa smbclk1 ieee_test1p/ rsvd_r13 ieee_test1n/ rsvd_t13 13 vssa vcc11 vcc11 vcc11 vssa smbd1 smbd0/flbmd smbclk0/ flbmck 12 vssa vssa vssa vssa vssa pe_waken smbalrt_n/ pci_pwr_good vcc33 11 vcc18 vcc18 vcc18 vcc18 vss flsh_ce_n flsh_sck vss 10 vcc11 vcc11 vcc11 vcc11 vcc33 led1_3/ rsvd_p9 flsh_so flsh_si 9 vss vss vss vss vss led1_0/ rsvd_p8 led1_1/ rsvd_r8 led1_2/ rsvd_t8 8 vcc11 vcc11 vcc11 vcc11 vcc33 flbsd flbintex nc_t7 7 vss vss vss vss vss sdp1_0/ rsvd_p6 sdp1_3/ rsvd_r6 pe_rstn 6 vcc11 vcc18 vssa vcc18 vcc11 jtdo test_en vcc33 5 vcc11 vcc18 vssa vcc18 vcc11 jtck rsvd vss 4 vssa vssa vssa vssa vssa jtms jtdi dev_off_n 3 pe_clkn pe_clkp vssa pern1 perp1 vssa pern0 perp0 2 rsvd_j1 vssa petn1 petp1 vssa petn0 petp0 vssa 1
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